Over the last few decades, the semiconductor industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices, and the most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor. The MOS transistor is one of the basic building blocks of most modern electronic circuits. Importantly, these electronic circuits realize improved performance and lower costs, as the performance of the MOS transistor is increased and as manufacturing costs are reduced.
A typical MOS semiconductor device includes a semiconductor substrate on which a gate electrode is disposed over a gate dielectric. The gate electrode, which acts as a conductor, receives an input signal to control operation of the device. Source and drain regions are typically formed in regions of the substrate adjacent the gate electrodes by doping the regions with a dopant of a desired conductivity. The conductivity of the doped region depends on the type of impurity used to dope the region. The typical MOS transistor is symmetrical, in that the source and drain are interchangeable. Whether a region acts as a source or drain typically depends on the respective applied voltages and the type of device being made. The collective term source/drain region is used herein to generally describe an active region used for the formation of either a source or drain.
The gate electrode is typically formed from polysilicon, and the resistivity of the polysilicon gate conductor is reduced by the introduction of impurities. After sufficient dopants are introduced into the gate electrode, the sheet resistance of the gate electrode can be reduced, in some instances, to less than approximately 500 ohms per square. When the dopants are introduced using an ion implantation process, the depth at which the dopants are implanted can be controlled by adjusting the energy provided to the ions by the ion implantation equipment. However, the minimum depth of implantation is limited to between about 200 and 400 angstroms because the energy of each ion is typically too large to permit a lesser depth of implantation.
Subsequent processing steps may require heating of the semiconductor topography. For example, a post-doping anneal is often performed to position and activate the dopants implanted into the source/drain regions and the gate electrode. Dopants with a high diffusivity typically migrate to greater depths within the polysilicon gate electrode than dopants with a lower diffusivity. For example, boron, which is commonly used to dope the polysilicon gate and the source/drain regions of an PMOS device, undergoes fast diffusion. On the other hand, arsenic, which is typically used to dope the polysilicon gate and the source/drain regions of a NMOS device, diffuses more slowly.
One problem with dopants, like boron, which readily migrate during heat treatment, are that the dopants may diffuse from the gate electrode, through the gate dielectric, and into a channel region of the transistor. The penetration of boron into the channel region can lead to undesirable effects. These effects include an increase in electron trapping, a decrease in low-field hole mobility, degradation of the transistor drive current, and increased sub-threshold current.
In an attempt to prevent the diffusion of impurities into the channel region, barrier atoms have been incorporated into the gate dielectric/channel interfacial region. For example, nitrogen is commonly introduced into the interfacial region by annealing the semiconductor topography in an ambient that includes NO, N2O or NH3 at temperatures between about 700 to 1000° C. Available N atoms may react with Si atoms and O atoms of the gate dielectric to form silicon oxynitride (“oxynitride”) to thereby terminate dangling bonds within the gate oxide. The presence of strong N—O bonds of oxynitride throughout the gate oxide also serve to reduce the entrapment of hot carriers within the gate oxide. Furthermore, single N atoms can block the migration pathways into and through the gate dielectric, thereby inhibiting fast diffusing impurities from passing from the gate electrode into the channel region.
Ion implantation of N atoms into the gate dielectric/channel interfacial region has also been employed as a barrier to hot carriers or to prevent species from passing into and out of the gate dielectric. Ion implantation involves accelerating the ions in an electric field to increase the energy of each ion to greater than 10 keV. Absent the ability to achieve lower energies for the ions, the ions are doped into a medium to a minimum depth of between about 200 and 400 angstroms. Accordingly, atoms implanted into the gate oxide are positioned and thereafter tend to migrate well below the gate dielectric/channel interface. These atoms, therefore, fill no interstitial and vacancy positions within the critical gate dielectric. Therefore, the atoms provide little, if any, barrier against the migration of impurities from the gate electrode into the channel and to the injection of hot carriers into the gate dielectric. Accordingly, a need exists for a more effective method for forming a diffusion barrier between the gate electrode and the channel region of a transistor to prevent the migration of dopants into the channel region and/or hot carriers into the gate dielectric.